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 急聘有海外工作经验的的IC人才 |
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作者：游客 在 海归商务 发贴, 来自【海归网】 http://www.haiguinet.com
各位朋友，你们好！
如果你有朋友适合，请立即让他寄简历到[email protected] 或来电1(650)365-4473
1,工作职位 经理
年薪 300000-400000 RMB以上 按综合能力可面议
工作地点： Xi'an/西安
公司简述 全球名列前矛半导体公司,以及第三大存储器供应商。
提供半导体解决方案，为21世纪人类创造个性化科技生活。
2002年全球销售总额突破52亿欧元。公司总部位于欧洲,
业务范围包括：有线通讯，安全移动方案，汽车和工业电子以及存储产品等。
公司目前在中国的业务涉及销售、技术支持、研发以及生产，在北京、上海、深圳以及无锡分别设有分公司及工厂。
主要从事芯片的研发业务，它将成为亚太地区的第一大研发中心。
诚邀IC领域的有志之才，本公司将提供有挑战性的工作机会、广阔的事业发展空间及完善的薪酬待遇。
工作简述 Project Manager
Salary: Negotiable
Responsibilities:
· Lead an IC Design project team
· Project effort evaluation
· Schedule Definition and execution
· Development budget definition and optimization
· Allocation of needed resources and skills
· Declaration of Infineon specific millstones respecting required
quality
· Interface between different groups
· Define IP delivery schedule
· Optimization of Cost-Quality-Yield
· Customers interface. Requirements:
· Phd/Masters/Bachelor’s Degree in Electrical/Electronics
Engineering
· Minimum 5 - 8 years of experience in IC design with at-least 3
years of experience as a Project manager.
· Should be very conversant with ASIC methodology and relevant EDA
tools used in the industry (Synthesis, Simulation, formal verification,
Static Timing Analysis, DFT, FE/BE interface etc) and should be hands-on to
resolve issues/suggest actions/initiate alternate-plans.
· Ensure regular reporting, documentation and should have excellent
communication and leadership skills.
· Tools skills:
· EDA tools knowledge
· Microsoft project
· Excel
· Word
· PowerPoint
Good compensation and Provide accommodation.
2,年薪 15万以上 可面议
工作简述 IC Physical Implementation (RTL2GDS) Engineer
Responsibilities:
· Writing, running, optimization of logical and physical synthesis scripts
· Optimization of area and Timing during synthesis
· Interface with System Design group: Timing constraints definition
· Post-Synthesis STA
· Script Optimization for Floorplanning
· Static power planning
· Routing considering timing constraints
· Parasitic extraction, conversion to Verilog including delay (gate-level)
· Post routing STA
· FE/BE STA correlation
· Physical Verification (DRC, ERC, LVS, ANTENNA)
· Formal verification
Requirements:
· Masters/Bachelor’s Degree in Electrical/Electronics Engineering
· > 5 years design experience (skills mentioned above)
· Tools skills:
· General tools (PowerPoint, Word, Excel, Acrobat, etc)
· Design Compiler/ Physical Compiler
· PERL, TCL languages
· PrimeTime
· VoltageStorm or any power routing analysis tool
· Magma or Apollo or any routing tools
· Calibre or Assura or any physical verification tool
· CVE or Formality or any formal verification tool
Good compensation and Provide accommodation.
3，工作简述 IC System Design Engineer
Responsibilities:
· Interface to concept engineering
· Design specification
· Define clock, reset and power concept
· System C verification (prototyping)
· Study and Integration of external IPs
· VHDL or Verilog Coding
· Test benches generation according to the different scenarios
· Functional validation
· Regression test
· Gate level simulation
· Static timing constraint definition
Requirements:
· Masters/Bachelor’s Degree in Electrical/Electronics Engineering
· > 5 years design experience (skills mentioned above)
· Tools skills:
· Matlab and Cossap knowledge is an advantage
· General tools (PowerPoint, Word, Excel, Acrobat, etc)
· PERL or SHELL languages
· Affirma or Modelsim
· Design Compiler or Physical Compiler
· PrimeTime
· TOPS
· Pattern integrator
Good compensation and Provide accommodation.
https://www.JMEP.com >结盟海外英才网
作者：游客 在 海归商务 发贴, 来自【海归网】 http://www.haiguinet.com
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 急聘有海外工作经验的的IC人才 -- jmep.com - (8216 Byte) 2003-7-25 周五, 00:35 (1185 reads)
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